; dot komodo file v 0.1.2 ; ARM v4, MIPS R3000 and STUMP (parts of 6809) instruction sets and processor descriptions ; You can allways get the latest version from: ; http://www.cs.man.ac.uk/~brejc8/.komodo ; to learn chump look at the descrition of STUMP at the bottom ; This part of the file is for use only with KMD and is ignored by chump ; Chump parts starts from about line 100 ( (cpu 1 0 0 "ARM" ; cpu architecture-number max-verion min-version (memory-ptr-width 4) ; width of memory poeinter (assumes 4) (wordaline 1) ; Are words word aligned? ; Too paindul to explain. ; (window-list "!~NCurrent.R0.User.R1.Supervisor.R2.Abort.R3.IRQ.R4.FIQ.R5|R6,R7~M~SC") ; (window-list2 (hpane ; (vpane (notepad ("Current" register (number 0)) ; ("User" register (number 1)) ; ("Supervisor" register (number 2)) ; ("Abort" register (number 3)) ; ("IRQ" register (number 4)) ; ("FIQ" register (number 5)) ; ) ; (hbox (register (number 6)) ; (register (number 7)) ; ) ; (position 370) ; ) ; (vpane ; (source) ; (vpane (memory) ; (comms) ; ) ; ) ; ) ; ) (window-list2 (hpane (vpane (register (number 0)) (register (number 6)) (position 350)) (vpane (source) (vpane (memory) (comms ) ) (position 250) ) ) ) (regbanks 0 ; regbanks main-regbank (regbank-granularity 4) ; regbank minimum transfare (regbank "Current" 18 4 0 ; regbank "name" number-of-registers size-of-registers offset (names "R0" "R1" "R2" "R3" "R4" "R5" "R6" "R7" "R8" "R9" "R10" "R11" "R12" "R13" "R14" ("PC" "R15") "CPSR" "SPSR") ) (regbank "System" 17 4 32 (names "R0" "R1" "R2" "R3" "R4" "R5" "R6" "R7" "R8" "R9" "R10" "R11" "R12" "R13" "R14" ("PC" "R15") "CPSR" "SPSR") ) (regbank "Supervisor" 18 4 64 (names "R0" "R1" "R2" "R3" "R4" "R5" "R6" "R7" "R8" "R9" "R10" "R11" "R12" "R13" "R14" ("PC" "R15") "CPSR" "SPSR") ) (regbank "Abort" 18 4 96 (names "R0" "R1" "R2" "R3" "R4" "R5" "R6" "R7" "R8" "R9" "R10" "R11" "R12" "R13" "R14" ("PC" "R15") "CPSR" "SPSR") ) (regbank "IRQ" 18 4 160 (names "R0" "R1" "R2" "R3" "R4" "R5" "R6" "R7" "R8" "R9" "R10" "R11" "R12" "R13" "R14" ("PC" "R15") "CPSR" "SPSR") ) (regbank "FIQ" 18 4 192 (names "R0" "R1" "R2" "R3" "R4" "R5" "R6" "R7" "R8" "R9" "R10" "R11" "R12" "R13" "R14" ("PC" "R15") "CPSR" "SPSR") ) (regbank "Current Flags" 4 0 540 (names "V" "C" "Z" "N") ) (regbank "Saved Flags" 4 0 572 (names "V" "C" "Z" "N") ) (regbank "Pointers" 16 4 0 (names "R0" "R1" "R2" "R3" "R4" "R5" "R6" "R7" "R8" "R9" "R10" "R11" "R12" "R13" "R14" ("PC" "R15")) (pointers) (PC 15) (RA 14) (SP 13) ) ) (isa "ARM32" "ARM16(Thumb)" "MIPS32") ;removed MIPS32 STUMP16 later ) (cpu 2 3000 0 "MIPS" (memory-ptr-width 4) (wordaline 1) (window-list "~M!M|R0,|R1,R2") (regbanks 0 (regbank-granularity 4) (regbank "CPU 0-15" 16 4 0 (names "R0" "R1" "R2" "R3" "R4" "R5" "R6" "R7" "R8" "R9" "R10" "R11" "R12" "R13" "R14" "R15" (pointers) ) ) (regbank "CPU 16-31" 16 4 16 (names "R16" "R17" "R18" "R19" "R20" "R21" "R22" "R23" "R24" "R25" "R26" "R27" "R28" "R29" "R30" "R31" ) (pointers) (RA 15) (SP 14) ) (regbank "CP0" 15 4 32 (names "index" "rand" "E_lo" "con" "bvadr" "e_hi" "sr" "cause" "prid" "HI" "LO" "dreg" "dval" "NEXTPC" "PC" ) (pointers) (PC 14) ) ) (isa "MIPS32") ) ; Now the chump descritopns start (isa "ARM32" ; Things Missing: CDP, LDRD, MCRR, MRRC, PLD, STRD (define "reg" ( enum 4 "R0" "R1" "R2" "R3" "R4" "R5" "R6" "R7" "R8" "R9" "R10" "R11" "R12" "R13" "R14" ("PC" "R15"))) ;R15 aliased with PC (define "rd" reg) (define "rn" reg) (define "rm" reg) (define "rs" reg) (define "rotimm" ((("imm" (uint 8))) ;immediate rotated field (OOOO imm)) ((("imm" (uint 8 @32 2))) (OOOI imm)) ((("imm" (uint 8 @32 4))) (OOIO imm)) ((("imm" (uint 8 @32 6))) (OOII imm)) ((("imm" (uint 8 @32 8))) (OIOO imm)) ((("imm" (uint 8 @32 10))) (OIOI imm)) ((("imm" (uint 8 @32 12))) (OIIO imm)) ((("imm" (uint 8 @32 14))) (OIII imm)) ((("imm" (uint 8 @32 16))) (IOOO imm)) ((("imm" (uint 8 @32 18))) (IOOI imm)) ((("imm" (uint 8 @32 20))) (IOIO imm)) ((("imm" (uint 8 @32 22))) (IOII imm)) ((("imm" (uint 8 @32 24))) (IIOO imm)) ((("imm" (uint 8 @32 26))) (IIOI imm)) ((("imm" (uint 8 @32 28))) (IIIO imm)) ((("imm" (uint 8 @32 30))) (IIII imm)) ) (define "shift" (("LSL") (OO)) ;Shift types (("LSR") (OI)) (("ASR") (IO)) (("ROR") (II)) ) (define "shiftop" ( (rm ) ;replace ROR 0 with RRX (OOOOO OOO rm) ) ( (rm ", RRX") (OOOOO IIO rm) ) ( (rm", " shift " #" ("imm" (uint 5))) (imm shift O rm) ) ( (rm", " shift " " rs) (rs O shift I rm) ) ) (define "arm_instruction" ;ARM 32 instruction set (define "condition" (("") (IIIO)) ;Conditions (("EQ") (OOOO)) (("NE") (OOOI)) (("CS") (OOIO)) (("HS") (OOIO)) (("CC") (OOII)) (("LO") (OOII)) (("MI") (OIOO)) (("PL") (OIOI)) (("VS") (OIIO)) (("VC") (OIII)) (("HI") (IOOO)) (("LS") (IOOI)) (("GE") (IOIO)) (("LT") (IOII)) (("GT") (IIOO)) (("LE") (IIOI)) (("AL") (IIIO)) ;AL aliased with "" (("NV") (IIII)) ) (define "opcode2" (("TST") (OO)) ;rn rm (("TEQ") (OI)) ;rn rm (("CMP") (IO)) ;rn rm (("CMN") (II)) );rn rm (define "opcode" (("AND") (OOOO)) ;3 (("EOR") (OOOI)) ;3 (("SUB") (OOIO)) ;3 (("RSB") (OOII)) ;3 (("ADD") (OIOO)) ;3 (("ADC") (OIOI)) ;3 (("SBC") (OIIO)) ;3 (("RSC") (OIII)) ;3 ; (("TST") (IOOO)) ;rn rm ; (("TEQ") (IOOI)) ;rn rm ; (("CMP") (IOIO)) ;rn rm ; (("CMN") (IOII)) ;rn rm (("ORR") (IIOO)) ;3 ; (("MOV") (IIOI)) ;2 (("BIC") (IIIO)) ;3 ; (("MVN") (IIII)) ;2 ) (define "set" (("S") (I)) (("") (O)) ) (define "sign" (("U") (O)) (("S") (I))) (define "relativerotimm" ((("imm" (urelative 8 - 8))) ;immediate rotated field relative (OOOO imm)) ((("imm" (urelative 8 @32 2 - 8))) (OOOI imm)) ((("imm" (relative 8 @32 4 - 8))) (OOIO imm)) ((("imm" (relative 8 @32 6 - 8))) (OOII imm)) ((("imm" (relative 8 @32 8 - 8))) (OIOO imm)) ((("imm" (relative 8 @32 10 - 8))) (OIOI imm)) ((("imm" (relative 8 @32 12 - 8))) (OIIO imm)) ((("imm" (relative 8 @32 14 - 8))) (OIII imm)) ((("imm" (relative 8 @32 16 - 8))) (IOOO imm)) ((("imm" (relative 8 @32 18 - 8))) (IOOI imm)) ((("imm" (relative 8 @32 20 - 8))) (IOIO imm)) ((("imm" (relative 8 @32 22 - 8))) (IOII imm)) ((("imm" (relative 8 @32 24 - 8))) (IIOO imm)) ((("imm" (relative 8 @32 26 - 8))) (IIOI imm)) ((("imm" (relative 8 @32 28 - 8))) (IIIO imm)) ((("imm" (relative 8 @32 30 - 8))) (IIII imm)) ) (define "relativerotimm_neg" ((("imm" (urelative 8 ~ 8))) ;immediate rotated field relative (OOOO imm)) ((("imm" (urelative 8 @32 2 ~ 8))) (OOOI imm)) ((("imm" (relative 8 @32 4 ~ 8))) (OOIO imm)) ((("imm" (relative 8 @32 6 ~ 8))) (OOII imm)) ((("imm" (relative 8 @32 8 ~ 8))) (OIOO imm)) ((("imm" (relative 8 @32 10 ~ 8))) (OIOI imm)) ((("imm" (relative 8 @32 12 ~ 8))) (OIIO imm)) ((("imm" (relative 8 @32 14 ~ 8))) (OIII imm)) ((("imm" (relative 8 @32 16 ~ 8))) (IOOO imm)) ((("imm" (relative 8 @32 18 ~ 8))) (IOOI imm)) ((("imm" (relative 8 @32 20 ~ 8))) (IOIO imm)) ((("imm" (relative 8 @32 22 ~ 8))) (IOII imm)) ((("imm" (relative 8 @32 24 ~ 8))) (IIOO imm)) ((("imm" (relative 8 @32 26 ~ 8))) (IIOI imm)) ((("imm" (relative 8 @32 28 ~ 8))) (IIIO imm)) ((("imm" (relative 8 @32 30 ~ 8))) (IIII imm)) ) (("BKPT" "\tf20" ((("immHi" 12) ("immLo" 4)) (uint 24)))( IIIO OOOIOOIO immHi OIII immLo)) (("NOP") (OOOOOOOO OOOOOOOO OOOOOOOO OOOOOOOO)) (("MRS" condition "\tf20" rd ", " ("psr" (("CPSR")(O)) ;e.g. MRS R0, CPSR (("SPSR")(I)) ) ) (condition OOOI O psr OO XXXX rd ZZZZ OOOO ZZZZ)) (("MSR" condition "\tf20" ("psr" (("CPSR")(O)) ;e.g. MSR SPSR_flags, 90000000 (("SPSR")(I)) ) ("mask"(("_flags") (IOOO)) (("_control") (OOOI)) (("_all") (IIII)) (("_none?") (OOOO)) (("") (IIII)) (("_unknown") (ZZZZ)) ) ", #" rotimm) (condition OOII O psr IO mask ZZZZ rotimm)) (("MSR" condition "\tf20" ("psr" (("CPSR")(O)) ;e.g. MSR SPSR_flags, R1 (("SPSR")(I)) ) ("mask"(("_flags") (IOOO)) (("_control") (OOOI)) (("_all") (IIII)) (("_none?") (OOOO)) (("") (IIII)) (("_unknown") (ZZZZ)) ) ", " rm) (condition OOOI O psr IO mask XXXX ZZZZ OOOO rm)) (("CLZ" condition "\tf20" rd ", " rm) (condition OOOI OIIO XXXX rd XXXX OOOI rm)) ((opcode2 condition "\tf20" ;2 operand no destination ops rn ;e.g. TST R2, #&12000 ", #" rotimm) (condition OOI IO opcode2 I rn ZZZZ rotimm)) ((opcode2 condition "\tf20" ;e.g. TST R2, R4, LSR #&1F rn ", " shiftop ) (condition OOO IO opcode2 I rn ZZZZ shiftop)) (( ("opp" (("MOV")(IIOI)) ;e.g. MOV R4, R7, ROR #&2 (("MVN")(IIII)) ) condition set "\tf20" rd ", #" rotimm) (condition OOI opp set ZZZZ rd rotimm)) ((("opp" (("MOV")(IIOI)) ;e.g. MOV R4, #&1200 (("MVN")(IIII)) ) condition set "\tf20" rd ", " shiftop) (condition OOO opp set ZZZZ rd shiftop )) (("ADR" condition "\tf20" rd ;e.g. ADR R4, lebel ", " relativerotimm) (condition OOI OIOO O IIII rd relativerotimm)) (("ADR" condition "\tf20" rd ;e.g. ADR R4, lebel ", " relativerotimm_neg) (condition OOI OOIO O IIII rd relativerotimm_neg)) ((opcode condition set "\tf20" rd ;e.g. ADD R4, R5, #&24000 ", " rn ", #" rotimm) (condition OOI opcode set rn rd rotimm)) ((opcode condition set "\tf20" rd ;e.g. SUB R4, R5, R4, ROR #&2 ", " rn ", " shiftop ) (condition OOO opcode set rn rd shiftop )) (("MUL" condition set "\tf20" rn ;e.g. MUL R3, R2, R12 ", " rm ", " rs) (condition OOO OOOO set rn ZZZZ rs IOOI rm )) (("MLA" condition set "\tf20" rd ;e.g. MLA R3, R2, R12, R2 ", " rm ", " rs ", " rn) (condition OOO OOOI set rd rn rs IOOI rm )) ((sign ("mul" (("MULL")(O)) ;e.g. SMULL R3, R2, R12, R2 (("MLAL")(I))) condition set "\tf20" rn ", " rd ", " rm ", " rs) (condition OOOO I sign mul set rd rn rs IOOI rm )) (define "ldst" (("STR")(O)) (("LDR")(I))) (define "byte" (("B")(I)) (("") (O)) ) (define "sub" (("-")(O)) (("") (I)) ) (define "pre" (("!")(I)) (("") (O)) ) (define "tran" (("T")(I)) (("") (O)) ) ((ldst condition byte "\tf20" ;e.g. LDRB R3, [#&145] rd ", [#" ("imm" (urelative 12 - 8)) "]" ) (condition OIOI I byte O ldst IIII rd imm)) ((ldst condition byte "\tf20" ;e.g. LDRB R3, [#&145] rd ", [#" ("imm" (urelative 12 ~ 8)) "]" ) (condition OIOI O byte O ldst IIII rd imm)) ((ldst condition byte "\tf20" ;e.g. LDRB R3, [R2]! rd ", [" rn "]" ) (condition OIOI X byte Z ldst rn rd OOOO OOOO OOOO )) ((ldst condition byte "\tf20" ;e.g. LDRB R3, [R2, #&123]! rd ", [" rn ", #" sub ("imm" (uint 12)) "]" pre ) (condition OIOI sub byte pre ldst rn rd imm)) ((ldst condition tran byte "\tf20" ;e.g. LDRB R3, [R2], #&123 rd ", [" rn "], #" sub ("imm" (uint 12)) ) (condition OIOO sub byte tran ldst rn rd imm)) ((ldst condition byte "\tf20" ;e.g. LDRB R3, [R2, -R3] rd ", [" rn ", " sub rm "]" pre ) (condition OIII sub byte pre ldst rn rd OOOO OOOO rm)) ((ldst condition tran byte "\tf20" rd ", [" rn "], " sub rm ) ;e.g. LDRB R3, [R2], -R3 (condition OIIO sub byte tran ldst rn rd OOOO OOOO rm)) ((ldst condition byte "\tf20" ;e.g. STR R4, [R3, R7, ROR #&2] rd ", [" rn ", " sub rm ", " shift " #" ("imm" (uint 5 / 2)) "]" pre ) (condition OIII sub byte pre ldst rn rd imm shift O rm)) ((ldst condition tran byte "\tf20" ;e.g. STR R4, [R3], R7, ROR #&2 rd ", [" rn "], " sub rm ", " shift " #" ("imm" (uint 5 / 2))) (condition OIIO sub byte tran ldst rn rd imm shift O rm)) (("SWP" condition byte "\tf20" ;e.g. SWP R5, R2, [R4] rd ", " rm ", [" rn "]") (condition OOOI O byte ZZ rn rd ZZZZ IOOI rm)) (define "sh" (("H") (OI)) (("SH") (II)) (("SB") (IO)) ) ((ldst condition sh "\tf20" ;e.g. LDRH R7, [R8] rd ", [" rn "]" ) (condition OOOI X I Z ldst rn rd OOOO I sh I OOOO)) ((ldst condition sh "\tf20" ;e.g. LDRH R7, [R8, #&13] rd ", [" rn ", #" sub ((("immHi" 4) ("immLo" 4)) (uint 8)) "]" pre ) (condition OOOI sub I pre ldst rn rd immHi I sh I immLo)) ((ldst condition sh "\tf20" ;e.g. LDRH R7, [R8], #&13 rd ", [" rn "], #" sub ((("immHi" 4) ("immLo" 4)) (uint 8)) ) (condition OOOO sub IO ldst rn rd immHi I sh I immLo)) ((ldst condition sh "\tf20" ;e.g. LDRH R7, [R8, -R4] rd ", [" rn ", " sub rm "]" pre ) (condition OOOI sub O pre ldst rn rd ZZZZ I sh I rm) ) ((ldst condition sh "\tf20" ;e.g. LDRH R7, [R8], -R4 rd ", [" rn "], " sub rm) (condition OOOO sub OI ldst rn rd ZZZZ I sh I rm)) (define "registerlist15" ((",PC") (I)) ;LDRM and STRM instructions ((",R15")(I)) (( ) (O)) ) (define "registerlists15" (("PC") (I)) (("R15") (I)) (("R14") (O)) ) (define "registerlist14" ((", R14-PC" )(II)) ((", R14-R15")(II)) ((", R14" ) (OI)) ((registerlist15 ) (registerlist15 O)) ) (define "registerlists14"(("R13" registerlist15 ) (registerlist15 O)) ((registerlists15 )(registerlists15 I)) ) (define "registerlist13" ((", R13-" registerlists15 )(registerlists15 II)) ((", R13" registerlist14 ) (registerlist14 I)) ((registerlist14 ) (registerlist14 O)) ) (define "registerlists13"(("R12" registerlist14 ) (registerlist14 O)) ((registerlists14 )(registerlists14 I)) ) (define "registerlist12" ((", R12-" registerlists14 )(registerlists14 II)) ((", R12" registerlist13 ) (registerlist13 I)) ((registerlist13 ) (registerlist13 O)) ) (define "registerlists12"(("R11" registerlist13 ) (registerlist13 O)) ((registerlists13 )(registerlists13 I)) ) (define "registerlist11" ((", R11-" registerlists13 )(registerlists13 II)) ((", R11" registerlist12 ) (registerlist12 I)) ((registerlist12 ) (registerlist12 O)) ) (define "registerlists11"(("R10" registerlist12 ) (registerlist12 O)) ((registerlists12 )(registerlists12 I)) ) (define "registerlist10" ((", R10-" registerlists12 )(registerlists12 II)) ((", R10" registerlist11 ) (registerlist11 I)) ((registerlist11 ) (registerlist11 O)) ) (define "registerlists10"(("R9" registerlist11 ) (registerlist11 O)) ((registerlists11 )(registerlists11 I)) ) (define "registerlist9" ((", R9-" registerlists11 )(registerlists11 II)) ((", R9" registerlist10 ) (registerlist10 I)) ((registerlist10 ) (registerlist10 O)) ) (define "registerlists9" (("R8" registerlist10 ) (registerlist10 O)) ((registerlists10 )(registerlists10 I)) ) (define "registerlist8" ((", R8-"registerlists10 )(registerlists10 II)) ((", R8" registerlist9 ) (registerlist9 I)) ((registerlist9 ) (registerlist9 O)) ) (define "registerlists8" (("R7" registerlist9 ) (registerlist9 O)) ((registerlists9 )(registerlists9 I)) ) (define "registerlist7" ((", R7-"registerlists9 )(registerlists9 II)) ((", R7"registerlist8 ) (registerlist8 I)) ((registerlist8 ) (registerlist8 O)) ) (define "registerlists7" (("R6"registerlist8 ) (registerlist8 O)) ((registerlists8 )(registerlists8 I)) ) (define "registerlist6" ((", R6-"registerlists8 )(registerlists8 II)) ((", R6"registerlist7 ) (registerlist7 I)) ((registerlist7 ) (registerlist7 O)) ) (define "registerlists6" (("R5"registerlist7 ) (registerlist7 O)) ((registerlists7 )(registerlists7 I)) ) (define "registerlist5" ((", R5-" registerlists7 )(registerlists7 II)) ((", R5" registerlist6 ) (registerlist6 I)) ((registerlist6 ) (registerlist6 O)) ) (define "registerlists5" (("R4" registerlist6 ) (registerlist6 O)) ((registerlists6 )(registerlists6 I)) ) (define "registerlist4" ((", R4-" registerlists6 )(registerlists6 II)) ((", R4" registerlist5 ) (registerlist5 I)) ((registerlist5 ) (registerlist5 O)) ) (define "registerlists4" (("R3" registerlist5 ) (registerlist5 O)) ((registerlists5 )(registerlists5 I)) ) (define "registerlist3" ((", R3-" registerlists5 )(registerlists5 II)) ((", R3" registerlist4 )(registerlist4 I)) ((registerlist4 )(registerlist4 O)) ) (define "registerlists3" (("R2" registerlist4 )(registerlist4 O)) ((registerlists4 )(registerlists4 I)) ) (define "registerlist2" ((", R2-" registerlists4 )(registerlists4 II)) ((", R2" registerlist3 )(registerlist3 I)) ((registerlist3 )(registerlist3 O)) ) (define "registerlists2" (("R1" registerlist3 )(registerlist3 O)) ((registerlists3 )(registerlists3 I)) ) (define "registerlist1" ((", R1-" registerlists3)(registerlists3 II)) ((", R1" registerlist2 )(registerlist2 I)) ((registerlist2 )(registerlist2 O)) ) (define "registerlist" (("R0-" registerlists2 ) (registerlists2 II)) (("R1-" registerlists3 ) (registerlists3 IIO)) (("R2-" registerlists4 ) (registerlists4 IIOO)) (("R3-" registerlists5 ) (registerlists5 I IOOO)) (("R4-" registerlists6 ) (registerlists6 II OOOO)) (("R5-" registerlists7 ) (registerlists7 IIO OOOO)) (("R6-" registerlists8 ) (registerlists8 IIOO OOOO)) (("R7-" registerlists9 ) (registerlists9 I IOOO OOOO)) (("R8-" registerlists10 ) (registerlists10 II OOOO OOOO)) (("R9-" registerlists11 ) (registerlists11 IIO OOOO OOOO)) (("R10-" registerlists12 ) (registerlists12 IIOO OOOO OOOO)) (("R11-" registerlists13 ) (registerlists13 I IOOO OOOO OOOO)) (("R12-" registerlists14 ) (registerlists14 II OOOO OOOO OOOO)) (("R13-" registerlists15 ) (registerlists15 IIO OOOO OOOO OOOO)) (("R14-PC") ( IIOO OOOO OOOO OOOO)) (("R14-R15") ( IIOO OOOO OOOO OOOO)) (("R0" registerlist1 ) (registerlist1 I)) (("R1" registerlist2 ) (registerlist2 IO)) (("R2" registerlist3 ) (registerlist3 IOO)) (("R3" registerlist4 ) (registerlist4 IOOO)) (("R4" registerlist5 ) (registerlist5 I OOOO)) (("R5" registerlist6 ) (registerlist6 IO OOOO)) (("R6" registerlist7 ) (registerlist7 IOO OOOO)) (("R7" registerlist8 ) (registerlist8 IOOO OOOO)) (("R8" registerlist9 ) (registerlist9 I OOOO OOOO)) (("R9" registerlist10 ) (registerlist10 IO OOOO OOOO)) (("R10" registerlist11 ) (registerlist11 IOO OOOO OOOO)) (("R11" registerlist12 ) (registerlist12 IOOO OOOO OOOO)) (("R12" registerlist13 ) (registerlist13 I OOOO OOOO OOOO)) (("R13" registerlist14 ) (registerlist14 IO OOOO OOOO OOOO)) (("R14" registerlist15 ) (registerlist15 IOO OOOO OOOO OOOO)) (("PC") ( IOOO OOOO OOOO OOOO)) (("R15") ( IOOO OOOO OOOO OOOO)) (("none?") ( OOOO OOOO OOOO OOOO)) (("") ( OOOO OOOO OOOO OOOO)) ) (define "ldst" (("STM")(O)) (("LDM")(I))) ((ldst condition ("u" (("D")(O)) ;e.g. LDMDA R3, {R2-R3, R5-R7, R10} (("I")(I)) ) ("p" (("A")(O)) (("B")(I)) ) "\tf20" rn pre ", {" registerlist "}" ("s" (( )(O)) (("^")(I)) ) ) (condition IOO p u s pre ldst rn registerlist)) (define "ldstc" (("STC")(O)) (("LDC")(I))) (define "cocond" (("2")(IIII)) condition ) (define "clong" (("L") (I)) (() (O)) ) (define "cop" (enum 4 "P0" "P1" "P2" "P3" "P4" "P5" "P6" "P7" "P8" "P9" "P10" "P11" "P12" "P13" "P14" "P15" )) ((ldstc cocond clong "\tf20" ;e.g. STC P1, R3, [R3] cop ", " rd ", [" rn "]") (cocond IIOZ Z clong Z ldstc rn rd cop OOOO OOOO)) ((ldstc cocond clong "\tf20" ;e.g. STC P1, R3, [R3, #&10] cop ", " rd ", [" rn ", #" sub ("imm" (uint 8 / 4)) "]" pre ) (cocond IIOI sub clong pre ldstc rn rd cop imm)) ((ldstc cocond clong "\tf20" ;e.g. STC P1, R3, [R3], #&-10 cop ", " rd ", [" rn "], #" sub ("imm" (uint 8 / 4))) (cocond IIOO sub clong I ldstc rn rd cop imm)) (define "mrccr" (("MCR")(O)) (("MRC")(I)) ) ((mrccr cocond "\tf20" ;e.g. MCR P1, R3, R10, R12 cop ", " rd ", " rn ", " rm) (cocond IIIO ZZZ mrccr rn rd cop ZZZ I rm)) (("B" ("type" (("X")(OI)) (("LX")(II)) (("XJ")(IO)) ) condition "\tf20"rm) (condition OOOI OOIO XXXX XXXX XXXX OO type rm )) ;e.g. BXJ R12 (("B" ("link" (enum 1 "L" "")) "X" condition "\tf20"rm) (condition OOOI OOIO ZZZZ ZZZZ ZZZZ OO link I rm )) ;e.g. BXEQ R12 (("BLX" "\tf20" ((("offsetLo" 1) ("offsetHi" 24)) (relative 25 - 8 / 2)) ) (IIII IOI offsetLo offsetHi )) (("B" ("link" (("L" )(I)) ;e.g. B &1232C0 (("")(O)) ) condition "\tf20" ("offset" (relative 24 - 8 / 4)) ) (condition IOI link offset)) (("SWI" condition "\tf20" ("number" (uint 24))) ;e.g. SWI 1232C0 (condition IIII number)) ) (define "align2" (align 2)) (define "align4" (align 4)) (define "data" (define "dcdlist" (()()) (( ", " ("dcd" (uint 32)) dcdlist) (dcdlist dcd)) ) ((align4 "DCD" "\tf20" ("dcd" (uint 32)) dcdlist) (align4 dcdlist dcd)) (define "dcwlist" (()()) (( ", " ("dcw" (uint 16)) dcwlist) (dcwlist dcw)) ) ((align2 "DCW" "\tf20" ("dcw" (uint 16)) dcwlist) (align2 dcwlist dcw)) (define "string" (( ("ascii" (ascii "\"" )) string) (string ascii)) (()()) ) (define "dcb" (uint 8) (("\"" ("ascii" (ascii "\"" )) string "\"") (string ascii))) (define "dcblist" (()()) (( ", " dcb dcblist) (dcblist dcb)) ) (("DCB" "\tf20" dcb dcblist) (dcblist dcb)) (define "dcqlist" (()()) (( ", " ("dcq" (uint 64)) dcqlist) (dcqlist dcq))) ((align4 "DCQ" "\tf20" ("dcq" (uint 64)) dcqlist) (align4 dcqlist dcq)) ) (define "new_label" (label some other text)) (define "new_comment" (comment some other text)) (define "label" ((new_label ":" ) (new_label)) (()())) (define "comment" (()()) ((";" new_comment) (new_comment))) ((align4 label "\t10" arm_instruction comment)(align4 label arm_instruction comment)) ((label "\t10" data comment)(label data comment)) ) (isa "ARM16(Thumb)" (define "thumb_instruction" ;ARM 16 (thumb) instruction set (define "reg" ( enum 3 "r0" "r1" "r2" "r3" "r4" "r5" "r6" "r7")) (define "regfull" (("PC")(IIII)) (("SP")(IIIO)) ( enum 4 "r0" "r1" "r2" "r3" "r4" "r5" "r6" "r7" "r8" "r9" "r10" "r11" "r12" "r13" "r14" "r15")) (define "rm" reg) (define "rn" reg) (define "rd" reg) (define "rs" reg) (define "imm3" (uint 3)) (define "imm5" (uint 5)) (define "imm8" (uint 8)) (define "imm5_4" (uint 5 / 4)) (define "imm8_4" (uint 8 / 4)) (define "imm7_4" (uint 7 / 4)) (define "offset8" (relative 8 - 4 / 2)) (define "offset11" (relative 11 - 4 / 2)) (define "offset22" (relative 22 - 4 / 2)) (define "cond" (("") (IIIO)) ;Conditions (enum 4 "EQ" "NE" "CS" "CC" "MI" "PL" "VS" "VC" "HI" "LS" "GE" "LT" "GT" "LE" "AL" "NV" ) (("HS") (OOIO)) (("LO") (OOII))) (define "opp" ( enum 4 "AND" "EOR" "LSL" "LSR" "ASR" "ADC" "SBC" "ROR" "TST" "NEG" "CMP" "CMN" "ORR" "MUL" "BIC" "MVN")) ((opp "\tf20" rd ", " rm) (OIOOOO opp rm rd)) (("ADD" "\tf20" rd ", " rn ", #" imm3) (OOOIIIO imm3 rn rd)) (("SUB" "\tf20" rd ", " rn ", #" imm3) (OOOIIII imm3 rn rd)) (("MOV" "\tf20" rd ", " rn ) (OOOIIIO OOO rn rd)) (("ADD" "\tf20" rd ", #" imm8) (OOIIO rd imm8)) (("SUB" "\tf20" rd ", #" imm8) (OOIII rd imm8)) (("ADD" "\tf20" rd ", " rn ", " rm) (OOOIIOO rm rn rd)) (("SUB" "\tf20" rd ", " rn ", " rm) (OOOIIOI rm rn rd)) (("ADD" "\tf20" ((("rdH" 1) ("rd" 3)) regfull) ", " regfull ) (OIOOOIOO rdH regfull rd)) (("MOV" "\tf20" ((("rdH" 1) ("rd" 3)) regfull) ", " regfull ) (OIOOOIIO rdH regfull rd)) (define "pcsp" (("PC")(O)) (("SP")(I))) (("ADD" "\tf20" rd ", " pcsp ", #" imm8_4) (IOIO pcsp rd imm8_4)) (("ADD" "\tf20" "SP, #" imm7_4) (IOIIOOOOO imm7_4)) (("SUB" "\tf20" "SP, #" imm7_4) (IOIIOOOOI imm7_4)) (("ASR" "\tf20" rd ", "rm ", #" imm5) (OOOIO imm5 rm rd)) (("LSL" "\tf20" rd ", "rm ", #" imm5) (OOOOO imm5 rm rd)) (("LSR" "\tf20" rd ", "rm ", #" imm5) (OOOOI imm5 rm rd)) (("B" cond "\tf20" offset8) (IIOI cond offset8)) (("B" "\tf20" offset11) (IIIOO offset11)) (("BKPT" "\tf20" imm8) (IOIIIIIO imm8)) (("SWI" "\tf20" imm8) (IIOIIIII imm8)) (("B" ("link" (("L")(I))(()(O))) "X" "\tf20" regfull) (OIOOOIII link regfull ZZZ)) (("CMP" "\tf20" rd ", #" imm8) (OOIOI rd imm8)) (("MOV" "\tf20" rd ", #" imm8) (OOIOO rd imm8)) (("CMP" "\tf20" ((("rdH" 1) ("rd" 3)) regfull) ", " regfull ) (OIOOOIOI rdH regfull rd)) (define "byte" (("") (O)) (("B")(I))) (define "ldrstr" (("LDR")(I)) (("STR")(O))) ((ldrstr byte "\tf20" rd ", [" rn ", " imm5_4 "]" ) (OII byte ldrstr imm5_4 rn rd)) ((ldrstr byte "\tf20" rd ", [" rn ", " rm "]" ) (OIOI ldrstr byte O rm rn rd)) (("LDR" "\tf20" rd ", [" pcsp ", " imm8_4 "]" ) (OIOO pcsp rd imm8_4)) ((ldrstr "H" "\tf20" rd ", [" rn ", " imm5_4 "]" ) (IOOO ldrstr imm5_4 rn rd)) ((ldrstr "H" "\tf20" rd ", [" rn ", " rm "]" ) (OIOI ldrstr OI rm rn rd)) (("LDRSB" "\tf20" rd ", [" rn ", " rm "]" ) (OIOIOII rm rn rd)) (("LDRSH" "\tf20" rd ", [" rn ", " rm "]" ) (OIOIIII rm rn rd)) (("STR" "\tf20" rd ", [SP, " imm8_4 "]" ) (IOOIO rd imm8_4)) (("BL" ("ex"(("X")(II))(()(OI))) "\tf20" ((("Hi" 11)("Lo" 11)) offset22)) (III IO Hi III ex Lo)) (define "registerlist7" ((",R7")(I)) (( ) (O)) ) (define "registerlists7" (("R7") (I)) (("R6") (O)) ) (define "registerlist6" ((", R6-R7")(II)) ((", R6" ) (OI)) ((registerlist7 ) (registerlist7 O)) ) (define "registerlists6" (("R5" registerlist7 ) (registerlist7 O)) ((registerlists7 )(registerlists7 I)) ) (define "registerlist5" ((", R5-" registerlists7 )(registerlists7 II)) ((", R5" registerlist6 ) (registerlist6 I)) ((registerlist6 ) (registerlist6 O)) ) (define "registerlists5" (("R4" registerlist6 ) (registerlist6 O)) ((registerlists6 )(registerlists6 I)) ) (define "registerlist4" ((", R4-" registerlists6 )(registerlists6 II)) ((", R4" registerlist5 ) (registerlist5 I)) ((registerlist5 ) (registerlist5 O)) ) (define "registerlists4" (("R3" registerlist5 ) (registerlist5 O)) ((registerlists5 )(registerlists5 I)) ) (define "registerlist3" ((", R3-" registerlists5 )(registerlists5 II)) ((", R3" registerlist4 )(registerlist4 I)) ((registerlist4 )(registerlist4 O)) ) (define "registerlists3" (("R2" registerlist4 )(registerlist4 O)) ((registerlists4 )(registerlists4 I)) ) (define "registerlist2" ((", R2-" registerlists4 )(registerlists4 II)) ((", R2" registerlist3 )(registerlist3 I)) ((registerlist3 )(registerlist3 O)) ) (define "registerlists2" (("R1" registerlist3 )(registerlist3 O)) ((registerlists3 )(registerlists3 I)) ) (define "registerlist1" ((", R1-" registerlists3)(registerlists3 II)) ((", R1" registerlist2 )(registerlist2 I)) ((registerlist2 )(registerlist2 O)) ) (define "registerlist" (("R0-" registerlists2 ) (registerlists2 II)) (("R1-" registerlists3 ) (registerlists3 IIO)) (("R2-" registerlists4 ) (registerlists4 IIOO)) (("R3-" registerlists5 ) (registerlists5 I IOOO)) (("R4-" registerlists6 ) (registerlists6 II OOOO)) (("R5-" registerlists7 ) (registerlists7 IIO OOOO)) (("R6-R7") ( IIOO OOOO)) (("R0" registerlist1 ) (registerlist1 I)) (("R1" registerlist2 ) (registerlist2 IO)) (("R2" registerlist3 ) (registerlist3 IOO)) (("R3" registerlist4 ) (registerlist4 IOOO)) (("R4" registerlist5 ) (registerlist5 I OOOO)) (("R5" registerlist6 ) (registerlist6 IO OOOO)) (("R6" registerlist7 ) (registerlist7 IOO OOOO)) (("R7" ) ( IOOO OOOO)) (("none?") ( OOOO OOOO)) (("") ( OOOO OOOO)) ) (define "ldrstr" (("LDMIA")(I)) (("STMIA")(O))) ((ldrstr "\tf20" rn registerlist) (IIOO ldrstr rn registerlist)) (define "poppush" (("POP") (I)) (("PUSH")(O))) (define "pc" ((", PC")(I)) (("") (O))) ((poppush "\tf20" "{" registerlist pc "}") (IOII poppush IO pc registerlist)) ) (define "align2" (align 2)) (define "align4" (align 4)) (define "data" (define "dcdlist" (()()) (( ", " ("dcd" (uint 32)) dcdlist) (dcdlist dcd)) ) ((align4 "DCD" "\tf20" ("dcd" (uint 32)) dcdlist) (align4 dcdlist dcd)) (define "dcwlist" (()()) (( ", " ("dcw" (uint 16)) dcwlist) (dcwlist dcw)) ) ((align2 "DCW" "\tf20" ("dcw" (uint 16)) dcwlist) (align2 dcwlist dcw)) (define "string" (( ("ascii" (ascii "\"" )) string) (string ascii)) (()()) ) (define "dcb" (uint 8) (("\"" ("ascii" (ascii "\"" )) string "\"") (string ascii))) (define "dcblist" (()()) (( ", " dcb dcblist) (dcblist dcb)) ) (("DCB" "\tf20" dcb dcblist) (dcblist dcb)) (define "dcqlist" (()()) (( ", " ("dcq" (uint 64)) dcqlist) (dcqlist dcq))) ((align4 "DCQ" "\tf20" ("dcq" (uint 64)) dcqlist) (align4 dcqlist dcq)) ) (define "label" ((("new_label" (label some other text)) ":" ) (new_label)) (()())) (define "comment" (()()) ((";" ("new_comment" (comment some other text))) (new_comment))) ((align2 label "\t10" thumb_instruction comment)(align2 label thumb_instruction comment)) ((label "\t10" data comment)(label data comment)) ) (isa "MIPS32" (define "regnum" (("0") (OOOOO)) (("1") (OOOOI)) (("2") (OOOIO)) (("3") (OOOII)) (("4") (OOIOO)) (("5") (OOIOI)) (("6") (OOIIO)) (("7") (OOIII)) (("8") (OIOOO)) (("9") (OIOOI)) (("10") (OIOIO)) (("11") (OIOII)) (("12") (OIIOO)) (("13") (OIIOI)) (("14") (OIIIO)) (("15") (OIIII)) (("16") (IOOOO)) (("17") (IOOOI)) (("18") (IOOIO)) (("19") (IOOII)) (("20") (IOIOO)) (("21") (IOIOI)) (("22") (IOIIO)) (("23") (IOIII)) (("24") (IIOOO)) (("25") (IIOOI)) (("26") (IIOIO)) (("27") (IIOII)) (("28") (IIIOO)) (("29") (IIIOI)) (("3O") (IIIIO)) (("31") (IIIII))) (define "reg" (("$" regnum)(regnum)) ;Annoyingly there are even more register naming convensions (("R" regnum)(regnum)) (("RA" )(IIIII )) ( enum 5 "zero" "at" "v0" "v1" "a0" "a1" "a2" "a3" "t0" "t1" "t2" "t3" "t4" "t5" "t6" "t7" "s0" "s1" "s2" "s3" "s4" "s5" "s6" "s7" "t8" "t9" "k0" "k1" "gp" "sp" "s8" "ra")) (define "rs" reg) (define "rt" reg) (define "rd" reg) (define "sa" reg) (define "and-link" (("AL") (I)) (("") (O)) ) (define "unsigned" (("U") (I)) (("") (O)) ) (define "special" (("MOVE" "\tf10" rd ", " rs) ;e.g. MOVE $4, $3 (rs OOOOO rd ZZZZZ IOOOO X)) (("NOP") (ZZZZZ ZZZZZ OOOOO ZZZZZ ZOOZZZ)) ;e.g. NOP ((( "op" ;e.g. SLL $4, $3, 11 (("SLL ") (OO)) (("SRL ") (IO)) (("SRA ") (II)) ) "\tf10" rd ", " rt ", " ("sa" (uint 5))) ( ZZZZZ rt rd sa OOOO op ) ) ((( "op" ;e.g. SLLV $4, $3, $5 (("SLLV ") (OO)) (("SRLV ") (IO)) (("SRAV ") (II)) ) "\tf10" rd ", " rt ", " rs) ( rs rt rd ZZZZZ OOOI op ) ) ((( "op" ;e.g. ADD $4, $3, $5 (("ADD" unsigned " ") (OOO unsigned)) (("SUB" unsigned " ") (OOI unsigned)) (("AND ") (OIOO)) (("OR ") (OIOI)) (("XOR ") (OIIO)) (("NOR ") (OIII)) (("SLT" unsigned " ") (IOI unsigned))) "\tf10" rd ", " rs ", " rt) ( rs rt rd ZZZZZ IO op ) ) (("JR " "\tf10" reg ) (reg ZZZZZ ZZZZZ ZZZZZ OOIOOO) ) ;e.g. JR $31 (("JALR " "\tf10" rs ", " rd) ;e.g. JALR $23, $31 ( rs ZZZZZ rd ZZZZZ OOIOOI) ) ((( "op" ;e.g. MUL $3, $2 (("MUL") (O)) (("DIV") (I))) unsigned "\tf10" rs ", " rt) ( rs rt ZZZZZ ZZZZZ OIIO op unsigned)) (("MF" ;e.g. MFHI $3 ( "mul-reg" (("HI ") (O)) (("LO ") (I))) "\tf10" reg ) ( ZZZZZ ZZZZZ reg ZZZZZ OIOO mul-reg O)) (("MT" ;e.g. MTLO $3 ( "mul-reg" (("HI ") (O)) (("LO ") (I))) "\tf10" reg) ( reg ZZZZZ ZZZZZ ZZZZZ OIOO mul-reg I)) (("SYSCALL") (ZZZZZ ZZZZZ ZZZZZ ZZZZZ OOIIOO)) ;e.g. SYSCALL (("BREAK") (ZZZZZ ZZZZZ ZZZZZ ZZZZZ OOIIOI)) ) ;e.g. BREAK (define "itype" (("LI " reg ", "("imm" (int 16))) (OOI OOOOO reg imm) ) ;e.g. LI $4, 123 ((( "op" ;e.g. ORI $4, $2, 123 (("ADDI" unsigned " ") (OO unsigned)) (("SLTI" unsigned " ") (OI unsigned)) (("ANDI ") (IOO)) (("ORI ") (IOI)) (("XORI ") (IIO)) (("LUI ") (III)))"\tf10" rt ", " rs ", " ("imm" (int 16))) ( op rs rt imm) ) ) (define "ldst" (( ("dir" ;e.g. LWC1 $4, 123($3) (("L") (O)) (("S") (I))) "WC" ("number" (uint 2)) "\tf10" rt ", " ("offset" (int 16)) "(" ("base" reg) ")") (I dir O number base rt offset)) (( ("dir" (("L") (O)) (("S") (I))) ( "size" ;e.g. LWL $4, 123($3) (("B" unsigned " ") (unsigned OO)) (("H" unsigned " ") (unsigned OI)) (("W ") (OII)) (("WL ") (OIO)) (("WR ") (IIO)) )"\tf10" rt", " ("offset" (int 16)) "(" ("base" reg) ")") (O dir size base rt offset)) ) (define "coprocessor" ((( "move" ;e.g. MFC0 $4, $2 (("M") (O)) (("C") (I))) ( "dir" (("F") (O)) (("T") (I))) "C" ("number" (uint 2)) "\tf10" rt ", " rd) (OO number OO dir move O rt rd OOOOOOOOOOO)) (("TLBR") (OOOOIOOOOOOOOOOOOOOOOOOOOOOOOI)) (("TLBWI") (OOOOIOOOOOOOOOOOOOOOOOOOOOOOIO)) (("TLBWR") (OOOOIOOOOOOOOOOOOOOOOOOOOOOIIO)) (("TLBP") (OOOOIOOOOOOOOOOOOOOOOOOOOOIOOO)) (("RFE") (OOOOIOOOOOOOOOOOOOOOOOOOOIOOOO)) (("COP" ("number" (uint 2)) "\tf10" ;e.g. COP1 123 ("code" (int 25))) (OO number I code)) (("BC" ("number" (uint 2)) ;e.g. BC1T 1000 ( "bool" (("F ") (O)) (("T ") (I))) "\tf10" ("offset" (relative 16 / 4 - 1))) (OO number OIOOO OOOO bool offset)) ) (define "brtype" (define "offset" (relative 16 / 4 - 1 )) (("B" and-link "\tf10" offset) ;e.g. BAL 30 (0 is positive) (OOI OOOOO and-link ZZZO offset)) (("B" "\tf10" offset) ;e.g. B 30 (0 = 0 ) (IOO OOOOO OOOOO offset)) ; For some reason GCC uses these reather than the ones above (("B" ( "cond" ;e.g. BLEZ $3, 20 (("LTZ") (O)) (("GEZ") (I))) and-link "\tf10" reg ", "offset) (OOI reg and-link ZZZ cond offset)) (("B" ( "cond" ;e.g. BEQ $3, $5, 20 (("EQ ") (O)) (("NE ") (I))) "\tf10" rs ", " rt ", " offset) (IO cond rs rt offset)) (("B" ( "cond" ;e.g. BLEZ $5, 20 (("LEZ ") (O)) (("GTZ ") (I))) "\tf10" reg ", " offset ) (II cond reg OOOOO offset)) ) ((special) (OOOOOO special )) (("J" and-link "\tf10" ("ptr" (int 26 / 4))) (OOOOI and-link ptr)) ((brtype) (OOO brtype )) ((itype) (OOI itype )) ((coprocessor) (OI coprocessor )) ((ldst) (I ldst )) (define "mips1" MIPS32) (define "mips2" MIPS32) (define "mips3" MIPS32) (define "compare_eq" (("=") (I)) (("==") (I)) (("!=") (O))) (define "not_compare_eq" (("=") (O)) (("==") (O)) (("!=") (I))) (("if (" rt not_compare_eq rs ")" "\t10" mips1 ";") ;e.g. if (r1 == r4) add r1,r1,r3; (mips1 OOOI O not_compare_eq rs rt OOOO OOOO OOOO OOOI )) (("if (" rt not_compare_eq rs ")" "\t10" "{" mips1 ";}") ;e.g. if (r1 == r4) {add r1,r1,r3;} (mips1 OOOI O not_compare_eq rs rt OOOO OOOO OOOO OOOI )) (("if (" rt not_compare_eq rs ")" "\t10" "{" mips1 ";" mips2 ";}") ;e.g. if (r1 == r4) {add r1,r1,r3; sub r1,r2,r1;} (mips2 mips1 OOOI O not_compare_eq rs rt OOOO OOOO OOOO OOIO )) (("if (" rt not_compare_eq rs ")" "\t10" "{" mips1 ";" mips2 ";" mips3 ";}") (mips3 mips2 mips1 OOOI O not_compare_eq rs rt OOOO OOOO OOOO OOII )) ;e.g. if (r1 == r4) {add r1,r1,r3; sub r1,r2,r1; and r1,r1,r4;} (("while (" rt not_compare_eq rs ")" "\t10" mips1 ";") (OOOO OIOO OOOO OOOI IIII IIII IIII IIOI mips1 OOOI O not_compare_eq rs rt OOOO OOOO OOOO OOIO )) (("while (" rt not_compare_eq rs ")" "\t10" "{" mips1 ";}") (OOOO OIOO OOOO OOOI IIII IIII IIII IIOI mips1 OOOI O not_compare_eq rs rt OOOO OOOO OOOO OOIO )) ;e.g. while (r1 != r4) {add r1,r1,r3;} (("while (" rt not_compare_eq rs ")" "\t10" "{" mips1 ";" mips2 ";}") (OOOO OIOO OOOO OOOI IIII IIII IIII IIOO mips2 mips1 OOOI O not_compare_eq rs rt OOOO OOOO OOOO OOII )) (("while (" rt not_compare_eq rs ")" "\t10" "{" mips1 ";" mips2 ";" mips3 ";}") (OOOO OIOO OOOO OOOI IIII IIII IIII IOII mips3 mips2 mips1 OOOI O not_compare_eq rs rt OOOO OOOO OOOO OIOO )) (("do" mips1 "; while (" rt compare_eq rs ")") (OOOI O compare_eq rs rt IIII IIII IIII IIIO mips1)) (("do {" mips1 ";} while (" rt compare_eq rs ")") (OOOI O compare_eq rs rt IIII IIII IIII IIIO mips1)) ;e.g. do {bl 10084;} while (r1 != r2) (("do {" mips1 ";" mips2";} while (" rt compare_eq rs ")") (OOOI O compare_eq rs rt IIII IIII IIII IIOI mips2 mips1)) (("do {" mips1 ";" mips2 ";" mips3 ";} while (" rt compare_eq rs ")") (OOOI O compare_eq rs rt IIII IIII IIII IIOO mips3 mips2 mips1)) (define "compare_sg" (("=0") (IOOO)) (("==0") (IOOO)) (("!=0") (IOIO)) (("<0") (OOII)) (("<=0") (IIOO)) ((">=0") (OOIO)) ((">0") (IIIO))) (define "not_compare_sg" (("=0") (IOIO)) (("==0") (IOIO)) (("!=0") (IOOO)) (("<0") (OOIO)) (("<=0") (IIIO)) ((">=0") (OOII)) ((">0") (IIOO))) (("if (" rs ((("compa" 3)("compb" 1)) not_compare_sg) ")" "\t10" mips1 ";") ;e.g. if (r1 > 0) add r1,r1,r3; (mips1 OOO compa rs OOOO compb OOOO OOOO OOOO OOOI)) (("if (" rs ((("compa" 3)("compb" 1)) not_compare_sg) ")" "\t10" "{" mips1 ";}") ;e.g. if (r1 > 0) add r1,r1,r3; (mips1 OOO compa rs OOOO compb OOOO OOOO OOOO OOOI)) (("if (" rs ((("compa" 3)("compb" 1)) not_compare_sg) ")" "\t10" "{" mips1 ";" mips2 ";}") ;e.g. if (r1 > 0) add r1,r1,r3; (mips2 mips1 OOO compa rs OOOO compb OOOO OOOO OOOO OOIO)) (("if (" rs ((("compa" 3)("compb" 1)) not_compare_sg) ")" "\t10" "{" mips1 ";" mips2 ";"mips3 ";}") ;e.g. if (r1 > 0) add r1,r1,r3; (mips3 mips2 mips1 OOO compa rs OOOO compb OOOO OOOO OOOO OOII)) ) (isa "STUMP16" ; STUMP is a simple 16bit processor (C) Andrew Bardsley ; Use this description to learn chump ; This is not a good tutorial but you can get the basics ; Firstly the basics: ; The following is the correct syntax to describe a translation ; (("Disasambled descrption")(Assambled description)) ; disassamled description is simply a string or set of strings ; Assembled description is a set of bits I (always on),O (always off), ; X (dontcare but set as on),Z (dontcare but set as off) ; Be careful, I and O are LETTERS. The parser will complain if it doesnt understand. ; e.g. 1 : (("R3")(OII)) - matches 011 to "R3" ; and "R3" to 011 ; e.g. 2 : (("BR")(OZX)) - matches 000, 001, 010 or 011 to "BR" ; and "BR" to 001 ; e.g. 3 : (("PC")(III)) ; (("R7")(III)) - matches 111, to "PC" as its first in the list ; and "PC" or "R7" to 111 ; e.g. 4 : (define "set" (("S")(I)) defines a rule called "set" ; (("") (O)) ) this rule can now be used in all rules below ; (("ADD" set) (OI set)) we can now use the predefined rule in another rule ; remember to place the rule in both the binary and ascii sections ; e.g. 5 : (define "imm" (int 4 + 4)) "imm" is defined to be a 4bit number. When DISASSEMBLING 4 is added ; e.g. 6 : (define "imm" (relative 4)) "imm" is defined to be a 4bit relative number offset from the current position ; e.g. 7 : (("#" ("imm" (int 4))) (imm)) the imm rule is defined in the rule. Its only valid in this rule ; and previous definition is ignored in this rule ; Take a look at the STUMP instruction set ; Instruction types ; 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 ; 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 ; -------------------------------- ; Type 1 OP |0|S| DST |SRCA |SRCB |SHIFT ; Type 2 OP |1|S| DST |SRCA | IMMEDIATE ; Cond Br 1|1|1|1| COND | OFFSET (define "reg" (("R0")(OOO)) (("R1")(OOI)) ; Firstly we 'define' a description of all the registers (("R2")(OIO)) (("R3")(OII)) ; R0 - 000, R1 - 001 ... PC - 111, R7 - 111 (("R4")(IOO)) (("R5")(IOI)) ; 111 is overloaded, When disassambling it will choose the first (("R6")(IIO)) (("PC")(III)) ; one ("PC") but when assembling either are acceptable (("R7")(III))) (define "dst" reg) ; DST is a register (define "srca" reg) ; so are SrcA and SrcB (define "srcb" reg) (define "op" (("ADD")(OOO)) (("ADC")(OOI)) ; These are the 6 OP codes (("SUB")(OIO)) (("SBC")(OII)) (("AND")(IOO)) (("OR") (IOI))) (define "set" (("S")(I)) ; If set bit is set then add an S onto the opcode (("") (O))) ; e.g. ADD -> ADDS (define "shift" (("") (OO)) ; Shift types ((", ASR") (OI)) ((", ROR") (IO)) ((", RRC") (II))) (define "cond" (("") (OOOO)) ; Branch conditions (("AL") (OOOO)) (("NV") (OOOI)) (("HI") (OOIO)) (("LS") (OOII)) (("CC") (OIOO)) (("CS") (OIOI)) (("NE") (OIIO)) (("EQ") (OIII)) (("VC") (IOOO)) (("VS") (IOOI)) (("PL") (IOIO)) (("MI") (IOII)) (("GE") (IIOO)) (("LT") (IIOI)) (("GT") (IIIO)) (("LE") (IIII))) (define "dir" (("LD")(O)) ; The difference between an ST and an LD is in the S bit (("ST")(I))) (("NOP") (OZZ Z O OOO ZZZ ZZZ ZZ)) ; These are the descriptions of the instructions (("NOP") (IOZ Z O OOO ZZZ ZZZ ZZ)) ; These two NOP descriptions overlap other instructions (("CMP" "\tf10" srca ", " srcb shift ) ; e.g. CMP R3, R6, ASR (OIO O I OOO srca srcb shift)) (("CMP" "\tf10" srca ", " ("imm" (int 5)) ) ; e.g. CMP R4, 12 (OIO I I OOO srca imm)) ; notice the inline definition if "imm" (("MOV" set "\tf10" dst ", " ("imm" (int 5))) ; e.g. MOVS R3, 12 (OOOO set dst OOO imm)) (("MOV" set "\tf10" dst ", " ( "src" ((reg)(OOO reg)) ; e.g. MOV R3, R5 ((reg)(reg OOO))) shift) ; note inline definition can also be translations (OOOO set dst src shift)) ((op set "\tf10" dst ", " srca ", " srcb shift) ; e.g. ADD R4, R7, R2 (op O set dst srca srcb shift)) ((op set "\tf10" dst ", " srca ", " ("imm" (int 5)) ) ; e.g. SUBS R6, R2, C (op I set dst srca imm)) (("B" cond "\tf10" ("offset" (relative 8 ))) ; e.g. BNE 100 (IIII cond offset)) ((dir "\tf10" dst ", [" srca ", " srcb shift "]") ; e.g. LD r4, [r3,r0] (IIO O dir dst srca srcb shift)) ((dir "\tf10" dst ", [" srca ", " ("imm" (int 5)) "]") ; e.g. LD r4, [r3,12] (IIO I dir dst srca imm)) ) (isa "MC6809" ; This is just a little tester to see if chump copes with CISC ISAs (define "aorb" (("A")(O)) (("B")(I))) (define "abopps" (("SUB") (OOOO)) (("CMP") (OOOI)) (("SBC") (OOIO)) (("AND") (OIOO)) (("BIT") (OIOI)) (("LD") (OIIO)) (("EOR") (IOOO)) (("ADC") (IOOI)) (("OR") (IOIO)) (("ADD") (IOII))) ( (("inherent" (("ASR")(OIII)) (("ASL")(IOOO)) (("CLR")(IIII)) (("COM")(OOII)) (("DEC")(IOIO)) (("INC")(IIOO)) (("LSL")(IOOO)) (("LSR")(OIOO)) (("NEG")(OOOO)) (("ROL")(IOOI)) (("ROR")(OIIO)) (("TST")(IIOI))) aorb) (OIO aorb inherent)) (("RTI") (OOIIIOII)) (("RTS") (OOIIIOOI)) (("SEX") (OOOIIIOI)) (("SWI") (OOIIIIII)) (("SWI2")(OOIIIIII OOOIOOOO )) (("SWI3")(OOIIIIII OOOIOOOO )) ((abopps aorb "\tf10" "#" ("imm" (uint 8))) (imm I aorb OO abopps)) ((abopps aorb "\tf10" "<" ("imm" (uint 16))) (imm I aorb II abopps)) ;;; FIXME / FINISHME ) (isa "Jamaica" (define "regnum" (("0") (OOOOO)) (("1") (OOOOI)) (("2") (OOOIO)) (("3") (OOOII)) (("4") (OOIOO)) (("5") (OOIOI)) (("6") (OOIIO)) (("7") (OOIII)) (("8") (OIOOO)) (("9") (OIOOI)) (("10") (OIOIO)) (("11") (OIOII)) (("12") (OIIOO)) (("13") (OIIOI)) (("14") (OIIIO)) (("15") (OIIII)) (("16") (IOOOO)) (("17") (IOOOI)) (("18") (IOOIO)) (("19") (IOOII)) (("20") (IOIOO)) (("21") (IOIOI)) (("22") (IOIIO)) (("23") (IOIII)) (("24") (IIOOO)) (("25") (IIOOI)) (("26") (IIOIO)) (("27") (IIOII)) (("28") (IIIOO)) (("29") (IIIOI)) (("3O") (IIIIO)) (("31") (IIIII))) (define "reg" (("%" regnum)(regnum)) (("R" regnum)(regnum)) ) (define "Ra" reg) (define "Rb" reg) (define "Rc" reg) (define "Opcode2" (("ADD") (OOO OOOO)) (("SUB") (OOO OOOI)) (("CMPEQ") (OOO OOIO)) (("CMPLE") (OOO OOII)) (("CMPLT") (OOO OIOO)) (("CMPULE") (OOO OIOI)) (("CMPULT") (OOO OIIO)) (("S4ADD") (OOO OIII)) (("S8ADD") (OOO IOOO)) (("S4SUB") (OOO IOOI)) (("S8SUB") (OOO IOIO)) (("AND") (OOO IOII)) (("BIC") (OOO IIOO)) (("BIS") (OOO IIOI)) (("EQV") (OOO IIIO)) (("ORNOT") (OOO IIII)) (("XOR") (OOI OOOO)) (("SLL") (OOI OOOI)) (("SRL") (OOI OOIO)) (("SRA") (OOI OOII)) (("CMOVEQ") (OOI OIOO)) (("CMOVGE") (OOI OIOI)) (("CMOVGT") (OOI OIIO)) (("CMOVLBC")(OOI OIII)) (("CMOVLBS")(OOI IOOO)) (("CMOVLE") (OOI IOOI)) (("CMOVLT") (OOI IOIO)) (("CMOVNE") (OOI IOII)) (("MUL") (OOI IIOO)) (("TRQ") (OOI IIOI)) (("RCR") (OOI IIIO)) (("WCR") (OOI IIII)) ) (define "OpRegRegDisp" (("LDA") (OOO OIO)) (("LDAH") (OOO OII)) (("LDL") (OOO IOO)) (("STL") (OOO IOI)) (("LDB") (OOO IIO)) (("LDBU") (OOO III)) (("STB") (OOI OOO)) (("LDL_L") (OOI OOI)) (("STL_C") (OOI OIO)) (("JSR") (OIO IOI)) (("JMP") (OIO IIO)) (("RET") (OIO III)) (("THJ") (OII OOI)) (("WAIT") (OII OIO)) ) (define "OpRegDisp21" (("BEQ") (OOI OII)) (("BGE") (OOI IOO)) (("BGT") (OOI IOI)) (("BLBC") (OOI IIO)) (("BLBS") (OOI III)) (("BLE") (OIO OOO)) (("BLT") (OIO OOI)) (("BNE") (OIO OIO)) (("BR") (OIO OII)) (("BSR") (OIO IOO)) (("THB") (OII OOO)) ) (define "imm8" (uint 8)) (define "disp21" (relative 21)) (define "imm16" (int 16)) ((Opcode2 "\tf10" Rc ", " Ra ", " Rb) (OOO OOI Ra Rb OOO O Opcode2 Rc)) ((Opcode2 "\tf10" Rc ", " Ra ", " imm8) (OOO OOI Ra imm8 I Opcode2 Rc)) ((OpRegRegDisp "\tf10" Ra ", " imm16 "(" Rb ")") (OpRegRegDisp Ra Rb imm16)) ((OpRegDisp21 "\tf10" Ra ", " disp21) (OpRegDisp21 Ra disp21)) ) (isa "transputer" (define "code" (("j") (OOOO)) (("ldlp") (OOOI)) (("pfix") (OOIO)) (("ldnl") (OOII)) (("ldc") (OIOO)) (("ldnlp") (OIOI)) (("nfix") (OIIO)) (("ldl") (OIII)) (("adc") (IOOO)) (("call") (IOOI)) (("cj") (IOIO)) (("awj") (IOII)) (("eqc") (IIOO)) (("stl") (IIOI)) (("stnl") (IIIO)) (("opr") (IIII)) ) (define "imm" (uint 4)) (("dup")(IIII IOIO OOIO OIOI )) (( code "\tf8" imm ) (code imm)) ) (isa "MU0" (define "new_label" (label some other text)) (define "new_comment" (comment some other text)) (define "label" ((new_label) (new_label)) (()())) (define "comment" (()()) ((";" new_comment) (new_comment))) (define "operator" (enum 4 "LDA" "STA" "ADD" "SUB" "AND" "OR" "JMP" "JGE" "JNE" "HALT" "INC")) (define "operand" (uint 12)) (define "data" (uint 16)) ((label "\t10" operator "\tf20" operand comment) (comment label operator operand)) ((label "\t10" data comment) (comment label data)) ) (feature 0x11 0x0a01 "xilinx-fpga" (name "Spartan XCS10XL") (XFPGA-filestring "s10xlvq100") ) (feature 0x12 0x1E02 "xilinx-fpga" (name "Virtex XCV300") (XFPGA-filestring "v300pq240") ) (feature 0x08 0x0 "console" (name "Console") ) )