What is it?Red Star is my next implementation of a MIPS R3000. (nothing to do with mips company legal bla bla bla)
It will be a stripped down and altered Yellow Star but then passed through my direct translation tool to make it asynchronous.
Why?Basically to demonstrate direct translation.
I'm hoping to get a speed improvement of at least 10% due to the switch to asynchronous logic.
What's different from Yellow Star?The pipeline is restructured to 5 full clock stages and only uses one clock edge.
Extra forwarding path.
No: TLB, cache, coprocessor, exception handling.
Fully harvard architecture (separate data and instruction memories).
No LWL/R SWL/R instructions as I was told off for even talking about them.
Oh yeah and the asynchronous version will have no clock!