Yellow Star (2001)
NEWS:Do you have experience in schematics? Would you like to convert the schematics to another package? (Cadence for example?) Please help.
Yellow Star was my third year project as a part of my B.Sc. degree from Manchester University. Yellow Star is an implementation of the 32 bit R2000/R3000 processor. I got all the information about the MIPS architecture I needed from"Mips RISC Architecture" By Gerry Kane and Joe Henrich I wish I could recommend the book but after months of working with it I have become tired of it and the whole MIPS architecture. I also used several web sites to find extra information not covered by the book.
I started off by finding a good pipeline to fit the
instruction set. Finally settling on this
As you can see it uses both sides of the clock which must be how the original MIPS processors were made. I have implemented every feature of the non interlocked pipeline like branch shadowing and load delays. A lot of the 'features' were a big clue as to the structure of the pipeline.
The R3000 isn't just a simple processor. It also includes exception handling, up to 3 Coprocessors, Memory management with a 64 entry fully associative TLB, independent instruction and data caches, 6 external interrupt lines, a kernel mode and a multiplyer/divider (not yet implemented). All enough to run a full operating system.
I have now finished the first beta version of the processor and tested it on this XESS Xilinx Vertex Board. As you can see it has a host of devices. I am hoping to implement an MP3 player loading the data from the Serial port and decoding it then playing using the Stereo Codec on board. Other ideas were to compile Linux to un on the board. As you can see there is a VGA port and a PS/2 port for the mouse. Unfortunately I have very little experience in this and I will probably start small.
This is a picture of the data path. You can see the data forwarding at the bottom and the Program Counter circuits at the top. The register bank is made from two copies of two phase (Write/Read) RAM banks to allow dual read and write access. The Shifter is constructed from 5 32bit multiplexers and a mask.
The MMU Is constructed from a 64 entry CAM. Unfortunately CAM is expensive on vertex devices so I created a 8x8 grid and placed a wired OR if any of the locations match then the address is reconstructed from the grid coordinates and passed to the RAM. This way only 27 bits need to be stored in the CAM rather than 64. This uses only 128 tristates rather than 4096.
full processor looks like this:
As you can see its quite a mess as I like to see the control on top level. Currently its just about to be tested running some code. An earlier version of the CPU was tested and run at 50MHz without errors. I am hoping to make a 100MHz version. The project is available at OpenCores. It is freely available to any person or company for any use but as a request could anyone using it please inform me of its application. There are instructions which are patented by MIPS and have been removed. Reimplementing them will break patents owned by MIPS. MIPS have noticed this project and have sent me threatening letters like this one. I advise you to set your compiler to not use them as MIPS will be very aggresive over their patent rights.
If you have any comments then E-Mail me at: CB at CS.MAN.AC.UK
Star 2003 is the processor I am currently working on. It is partly
based on yellow star but asynchronous. It is created by taking the synchronous
design and using direct translation to convert it to asynchronous form.
*Yellow Star is not a MIPS processor and is not MIPS processor compatible.
MIPS(R), R2000(R)and R3000(R) are registered trademarks of MIPS Technologies, Inc. in the United States and other countries. OpenCores and Charles Brej are not affiliated in any way with MIPS Technologies, Inc.