Utopium (nearly there)

Utopium has been sitting waiting to be manufactured for ages now but everything that can go wrong, has. Firstly I was targeting the 65nm process but just as I got ready to choose a manufacturing date, Europractice decided to pull all the remaining 65nm runs for the year. So I migrated the design to the 130nm technology. Unfortunately the date was also being used by the Spinica project for their test chips, which would have been fine, but there would have been a bit of competition for the CAD resources and for Jeff. After waiting another two months, Eustace and Steve started laying the design out. Here the CAD tools started to go crazy and running out of memory because of the many logical loops in the design.

dieplotAfter battling the tools for over a month, Jeff came in to attempt the design with Astro (a much older toolset). With two weeks before tape-out, the whole design was laid-out from scratch. It is always worrying when you have a process consuming 1.8 of your 2GB of RAM, but somehow everything went to plan and we had a final design on the final day. Inset is a die plot of the final design. Just as we all breathed a sigh of relief at the fact the design was sitting on the manufacturer’s ftp server with hours to spare, we received an email saying “sorry but we dropped your design, no more space”. If there are commercial customers, they pay more and thus get preference if they run out of space.

To their credit we were given the option of joining another run two months later. So that is where we are now, the new tape-out is on November the 30th. At that point Doug asks for more features on the design to make it easier to get relative results. So at the beginning of this week, I finally made the last verilog dump and Jeff has been doing the hopefully last layout. This time we should be several weeks early so it will be more difficult for them to drop our design.

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