Archive for the ‘ Async ’ Category

Utopiums are back

After months being manufactured, the Utopiums are back! I will explain more about what they are in another post, but for now here are some photos.

Here are the packaged chips (20 of).

They also send you the remaining unpackaged dies. These have an excellent ability of confusing the camera’s auto focus.

The full die is 5mm by 3mm.

And this is what they look like under a microscope. They do get dirty very quickly when exposed to a dusty room.

On the bottom right of the chip logo are the thank-yous. The Tux and the Fedora logo are about 0.5 mm tall (perhaps the smallest ever?). You can see the diffraction grating giving a nice secondary colour.

At different angles, they look very different.

And here is a wise comment left by the one of the Async symposium reviewers.

I am still testing the beast, but it does work. It has executed a number of programs and the wagging slices do become by-passable. The biggest worry was the reset as that is quite complicated, but it seems fine. I will open source the design and the tool set some time next month.

Utopium test board

I was expecting the Utopium to come back any minute now, but it appears when the fab says 11 to 12 weeks, they don’t mean from the tape-out date, they mean from some other date a month after (Grrrr). As I was expecting it this week, I made a board that it can sit in. If it works I will make a proper PCB with connections to peripherals, but in the mean time what I need is a platform from which I can observe and control every pin on the chip. Here are the ingredients.

This used to be Matt’s desk but it has been converted into my hardware geekery desk. The scope is a fantastically expensive one that I am currently using as a voltmeter.

First job was making a cable. The I have plenty of these IDE cables around. Splitting it into two and clipping some connectors, I now have 40 way to two 20 ways that fit into Jim’s lab board.

This is version 3 of the Jim’s lab board. The first one was back in 1999 when I started writing KMD. These boards have a default FPGA configuration which memory maps the I/O pins. This is ideal if you don’t to get into FPGA development just to get something simple going. Everything can be controlled from software running on the ARM.

I’m sure we probably have may of these three pin connectors in the electronics cabinets, but since I had an old broken motherboard on the desk, I thought this was easier.

The solder used on motherboards has a much higher melting point which can be annoying when removing larger though board components, but this wasn’t that bad. For large components I recommend placing the board onto an electric kitchen hob hotplate, then after a minute, turning it over and hitting to make all the parts fall out (ventilated room and a mask is probably in order here).

For signal wiring I use a Vero pen. These are fantastic. They are very thin, insulated wires which you wrap a couple times around the connected pins, then use solder to melt off the insulation. The insulation makes the solder point a bit dirty, but meh, they’re connected. Just dont show it to engineers, they suck their teeth and explain how they wouldn’t do it that way and start sentences with the words “Back in my day…”.

The danger of the Vero wire is that you can get it too hot while soldering a point near it and form a connection. The power connections were made using thicker wire.

And nearly one hundred solder points later we have a simple board. The ZIF socket is for a 48 pin DIL. These look weirdly long, as will the Utopium, when it comes back.

Happily connected to the Jim board, and tested for any shorted connections. I did this by flipping the I/O pins about. If you get values stuck half way between the rails, then something is shorted. This happened to me, but luckily the FPGA was quite robust to short connections and it worked fine after correcting it.

Here is a PIC in the socket. You can see how much longer the Utopium will be.

Well, one month left until she comes back. Can’t wait.

Utopium (nearly there)

Utopium has been sitting waiting to be manufactured for ages now but everything that can go wrong, has. Firstly I was targeting the 65nm process but just as I got ready to choose a manufacturing date, Europractice decided to pull all the remaining 65nm runs for the year. So I migrated the design to the 130nm technology. Unfortunately the date was also being used by the Spinica project for their test chips, which would have been fine, but there would have been a bit of competition for the CAD resources and for Jeff. After waiting another two months, Eustace and Steve started laying the design out. Here the CAD tools started to go crazy and running out of memory because of the many logical loops in the design.

dieplotAfter battling the tools for over a month, Jeff came in to attempt the design with Astro (a much older toolset). With two weeks before tape-out, the whole design was laid-out from scratch. It is always worrying when you have a process consuming 1.8 of your 2GB of RAM, but somehow everything went to plan and we had a final design on the final day. Inset is a die plot of the final design. Just as we all breathed a sigh of relief at the fact the design was sitting on the manufacturer’s ftp server with hours to spare, we received an email saying “sorry but we dropped your design, no more space”. If there are commercial customers, they pay more and thus get preference if they run out of space.

To their credit we were given the option of joining another run two months later. So that is where we are now, the new tape-out is on November the 30th. At that point Doug asks for more features on the design to make it easier to get relative results. So at the beginning of this week, I finally made the last verilog dump and Jeff has been doing the hopefully last layout. This time we should be several weeks early so it will be more difficult for them to drop our design.

Snobbery and the such

The talks to the group went reasonably well. I presented a very brief overview of the Utopium and presented some more amusing thoughts as to how science should be conducted. If you were not there this is a short list of topics covered: Apple fan-boys, fair-trade organic cocaine, Socrates questioning fries McDonald’s, a delicious cup of tea with hemlock, usage of tabs in indentation styles, the temperature of flames, employment being for the stupid, talk of bullocks, letching, Hitler, fish with springs for legs, buckteeth and glasses styles, drinks machines in the middle of a desert, Stalin surrounded by lovely ladies, glorious five year plan, a race between Che Guevara, Darwin and a snob, “the great cleansing” (killing of everyone over the age of 18), Windows 7 and spelling mitsakes in blogs.

Project Utopium Continued

Drudgery continues as I try to complete the Utopium instruction set. Current progress:


So some 38 instructions to go. The speed has now dropped to 26MIPS and the gate count is now up to 17000 (woot! sigh).I did something stupid in spreading the instruction data to the different units (instruction length decoder, data memory controller and ALU …), instead of having a single block decoding the instruction and controling them all, as now I have the same decode logic repeated in 3 places. This isn’t a huge overhead but but it does mean that I end up writing a lot more code. Just waiting till I complete the instruction set before I start inserting the half buffers. Still to come are the stack operations (push, pop, call and ret). The rest is external so that can wait.

Project Utopium

For just over two weeks now I have been designing an asynchronous processor. The working name is “Utopium” (a play on “Lutonium“). It’s an 8051 Currently I am completing the instruction set.

There is a nice instruction set table I am using to mark which instructions it can currently execute. Everything highlighted in pink is done. This was the state on the 6th of February:


This was the state on the 11th of February:


And finally this is now (13th February):


The easy common instructions are done, so that just leaves the reather nasty ones which will be like pushing a pea up a mountain using my nose. So far I learned two things:

  1. The 8 bit micros were designed by either a higher power which I cannot hope to comprehend, or they are a result of top secret illegal government experiments involving LSD and computer engineers.
  2. I should have used the highlighter with most ink.

So far it is 13,948 gates but that should hopefuly go down a bit once I do slightley more intelligent caches although it will also go up once I implement all the instructions. And the performance is a fantastic 30 MIPS which will go up quite a bit once I add the half bufffers.

Asynchronous processor speeds

asyncspeedsSomething that people keep stating which is an outright lie is that asynchronous logic is great for performance and that recent research is making it better and better. Numbers such as “4.6x to 20x” improvement are thrown around as if they mean something. The truth is (sadly) that asynchronous designs are stuck in the early 90s when it comes to performance. The graph shows the number of inversion delays per instruction on a range of intel processors (in red) versus the ones from the asynchronous community (in blue). Because the numbers are technology independent, you can make a fair comparison of the designs should they be implemented on the same technology. The asynchronous designs are now a factor of 10 behind. On the positive side, because the asynchronous community is so far behind, the 1 million transistor designs are minute in comparison to the industry leading 1 billion transistor implementations.

Area is not an issue, asynchronous designs are so far behind we can happily throw area at the problems and continue to do so for a good while. While with performance, lets face it, it is damn poor and creating and recreating the same poor performance designs and then claiming they are several times faster than the incredibly slow designs (see far left of the graph) is fruitless.